The subject matter of this invention pertains to computer systems, and more particularly, to an apparatus and method for releasing or freeing an input/output bus very early during a direct memory access (DMA) storage (read or write) operation.
In the above referenced patent application Ser. No. 909,431, a computer system is disclosed having a plurality of input/output buses each termed an "SPD" bus. Each SPD bus connects a number of "Input/Output Bus Units" or "Input/Output Processors" (IOBU or IOP) to an "Input/Output Interface Controller" (IOIC). Each IOIC, in turn, is connected to a common storage facility (memory) via (1) another bus, called the "adapter" bus; (2) a "Storage Controller", which includes an arbiter logic, an input/output interface unit, and a storage control logic; and (3) a "storage bus" or "memory bus". This computer system is generally illustrated in block form in FIG. 1.
During storage operations in this system from an IOP (connected to a particular SPD bus) to the common memory, the IOP sends data to memory via its associated SPD bus and waits for the return of storage status information indicative of the successful (or unsuccessful) storage of the data in the memory. During this waiting period, the particular SPD bus is "busy" and otherwise not available for use by any other IOP connected that SPD bus. Although for relatively small computer systems having only one or two IOIC's connected to the adapter bus and only a few IOP's connected to each SPD bus, the waiting period may be negligible, as the systems increase in size, the so-called "storage latency" time involved in transmitting data from an IOP to memory, or from memory to an IOP, increases to the point of detrimentally effecting the performance of the input/output portion of the computer system.
"Storage latency", as this term is used herein, is defined as that period of time from the moment that an IOP makes a request, through the SPD bus, to either place data into the computer memory or to get data from the computer memory to the moment when the storage status, and in some cases the data, is returned indicating that the data has been successfully (or unsuccessfully) transferred to or from memory. Stated another way, the storage latency period starts from the time that a storage operation is requested by the IOP and terminates when the results of the storage operation are being sent back to the IOP.
As a specific example, let us assume that an IOP initiates a request to transfer data to the common computer system memory via the direct memory access route which includes the SPD bus, its associated IOIC, the adapter bus, the storage controller, the memory bus and the computer memory. This operation will be variously referred to hereinafter as a "Storage Write", "DMA Write" or "Remote Read" operation. A request is initially made by the IOP to the IOIC via the associated SPD bus. The IOIC then requests access to the adapter bus. After obtaining access, the data is transmitted via the adapter bus to the storage controller which, in turn, stores the data in memory via the memory bus and then returns bus storage status via the adapter bus indicating the successful or unsuccessful completion of the storage operation. The storage status is relayed by the IOIC via the SPD bus to the requesting IOP.
Storage latency, in this storage write example, includes the time that the IOIC is active; namely, the period of waiting for access to the adapter bus; the period of transmitting the data via the adapter bus to the storage controller; the period of waiting for access to the memory bus; the period during which the data is actually stored in memory; the period of waiting (by the storage controller) for access to the adapter bus; and the period during which the storage status is returned via the adapter bus. A timing diagram showing this storage latency period is represented in FIG. 1a.
Similarly, an IOP can initiate a request to transfer data from the common computer memory via the direct memory access route to this IOP. This operation will be variously referred to hereinafter as a "Storage Read" "DMA Read" or "Remote Write" operation. In this case a request is initially made by the IOP to the IOIC via the associated SPD bus. The IOIC then requests access to the adapter bus. After obtaining access, the request is relayed via the adapter bus to the storage controller which, in turn, requests access to the memory bus. After obtaining access the storage controller reads the requested data from memory via the memory bus. The storage controller then requests and obtains access to the adapter bus and transfers data to the requesting IOIC. The IOIC then relays the data via the SPD bus to the requesting IOP.
Storage latency, in this storage read example, again includes the time that the IOIC is active; namely, the period commencing from the time of receipt of the request for data from an IOP to the time that this data is received from memory for transmission to the IOP. A timing diagram showing this storage latency period is represented in FIG. 1b.
As may be seen in FIGS. 1a and 1b, the storage latency period does not include the periods during which data and control information are transferred on the SPD bus. Rather, the storage latency time consists of the initial period of "waiting" for access to the adapter bus plus the time that the system takes to complete a read or write operation in memory once the adapter bus has been accessed. The waiting period for access to the adapter bus is indeterminately long depending upon the presence and priority of the IOIC's which are requesting and using the adapter bus. The time required to complete a read or write operation is also indeterminately long depending upon the amount of data to be transferred and upon whether the memory is otherwise occupied, for example in the execution of read/write operations initiated by the instruction processing unit of the computer system.
In the computer system disclosed in the aforementioned U.S. patent application Ser. No. 909,431, once a particular IOP requests and obtains access to the SPD bus, either to request a transfer of data to the memory or request a transfer of data from the memory, the SPD bus becomes dedicated to that IOP until such time as the entire operation is complete, including the transfer of data and storage status.
In addition, prior to sending data and control information between the IOP and memory, it is necessary to undergo a select cycle in preparation for the transmission of this data and information. When the final status information is received from memory indicating completion of the storage operation, the current SPD bus operation is terminated. If further data and information are to be transmitted from the IOP to memory, or vice versa, the computer system again undergoes a select sequence to initiate the transmission of the further data and information. Thus, the only time a second IOP can gain access to the SRD bus is at the end of a completed DMA.
This technique is very wasteful of the throughput capabilities of the SPD bus and thereby creates the need for a system that can utilize the SPD bus during periods of storage latency.